Balachander N. Verilog. Frequently Asked Questions 2004

Textbook in PDF format

We assume that the user has a very basic familiarity with the Verilog HDL. Readers who have a basic or intermediate level of expertise in the language can also refer to this book to know more implementation details of using the HDL in the different contexts of design, verification and implications to synthesis, static timing, etc. In this book, the authors have delved into many different front end topics of RTL such as synthesis, area, power, testability, etc. Most issues typically encountered during these stages have been presented in the form of FAQs. Whenever there is more than one approach to meet a requirement, the pros and cons of each approach are presented. We hope the book will also interest students who are learning Verilog for
the first time. We believe that this book provides answers to many questions that normally pop up as students begin to use the language. This book deals only with the front end issues, i.e., until completion of functional verification and synthesis with estimated wiring information. The book does not discuss any back-end issues like placement, floor-planning, or routing. The back-end processes are highly customized to the tools that implement them. Wherever appropriate, the implications of the coding style that would have an effect on the back-end steps are illustrated. This helps avoid expensive iterations in revisiting the golden code, in order to eliminate these back-end gotchas